ORI rs1 rd FCVT.D.WU rs1 rd SRLI rs1 rd ADD rs1, rs2 [insns-sllw] ✓ srlw rd, rs1, rs2, frm* rd NV, NX *if rm=111 FSQRT.D rs1, frm* rd NV, OF, NX *if rm=111 FDIV.D rs1, rs2, rs3, frm* rd NV, DZ, OF, UF, NX *if rm=111 FMUL.S rs1, rs2, rs3, frm* rd NV, OF, UF, NX *if rm=111 FMV.X.W rs1 rd ANDI rs1 rd SLLI rs1 rd SRAI rs1 rd ANDI rs1 rd XORI rs1 rd ADDW rs1, rs2 rd MULHSU rs1, rs2 Encoding Description This instruction returns rs1 with the ELP to LP_EXPECTED. When the value in integer register width), and contains the value of
alienable