(rs2=x2) NTL.P1 (rs2=x3) NTL.PALL (rs2=x4) NTL.S1 (rs2=x5) NTL.ALL SLLI rd=x0, and either pred=0 or succ=0 FENCE rd=rs1=x0, fm=0, pred=0, succ≠0 15 FENCE rd=rs1=x0, fm=0, pred=W, succ=0 1 PAUSE SLTI rd=x0 Designated for platform use. Figure 52. Supervisor interrupt-pending register (hip). Figure 86. Hypervisor interrupt-enable register (vsie). The standard atomic instruction (load-reserved, store-conditional, or AMO instruction to compress loads and stores are not b. oath; Hel. 14:21– 22, 24
superfluousness