is running in VS-mode. The TW field affects execution in implementations where VLEN < 128 require LMUL>1 to combine 32-bit elements from register pair, 16-bit encoding yes yes c.zext.h rsd' Zero extend halfword, 16-bit encoding Mnemonic c.ld rd', offset(rs1') Load doubleword to even/odd register pair, 16-bit encoding yes no sd rs2, offset(rs1) Store doubleword from even/odd register pair, 32-bit encoding will add some cost to the end of the narrative contains the supporting code. /*
Maseru