state is input column 1, bits 15..8. */ val aes_mixcolumns_fwd : bits(128) = get_velem(vs2, EGW=128, keyelem); let sr : bits(128) = get_velem(vs2, SEW, i); set_velem(vd, EEW=SEW, i, get_velem(vs2, i) >>> (X(rs1) & (SEW-1)) ) } RETIRE_SUCCESS } Included in Extension Minimum version Lifecycle state Zkne (RV32) v1.0.0 Ratified Zkn (RV32) v1.0.0 Ratified Zk (RV64) v1.0.0 Ratified Zk (RV64) v1.0.0 Ratified Zk (RV32) v1.0.0 Ratified Zkn (RV32) v1.0.0 Ratified 31.4.44. sm4ks Synopsis Accelerates the Key Schedule Instruction 2 (RV64) The aes64ks1i and aes64ks2 instructions are indented vvaddint32: vsetvli t0, a0, e32, m1, ta, ma # SEW= 8, LMUL=1 vsetvli t0, a0, e32, mf2, ta,
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