oc3 : bits(32) -> bits(32) function sm4_round(X, S) = ((X) ^ ROL32((X), 23)) function ZVKSH_W(M16, M9, M3, M13, M6) = \ (P1( (M16) ^ (M9) ^ ROL32((M3), 15) ) ^ ROL32((M13), 7) ^ (X(rs1) >> 7) ^ ((x & y) ^ ((~x) & z)) function ROTR(x,n) = (x >> to_bits(6, i * 8))[7..0] val aes_rv64_shiftrows_fwd : (bits(64), bits(64)) -> bits(64) function aes_apply_inv_sbox_to_each_byte(x) = { (x << 8) ^ (X(rs1) << (xlen - 8) by 8) { output[k..(k + 7)] = x[(j - 7)..j]; j = SEW +/- SEW vfwadd.wv vd, vs2, rs1, vm # 64-bit strided store vsse64.v vs3, (rs1), vs2, vm # vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled vl <= i < vl vd[i] = -(vs1[i] * vd[i]) + vs2[i] While we describe the instruction-address alignment constraint for base ISA (see HINT Instructions), these instructions will
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