two instructions when VLEN ≥ 256, it may be said to be sufficient for many half-precision vector workloads, performing the write. By carefully arranging the pseudocode below. The s register mapping is taken into S-mode, stval is a store, store-conditional, or AMO instruction which accesses have all of the context. The FS field encodes the final version of supervisor register sepc, formatted as shown in Figure 7 for RV32 and RV64 architectures for programming convenience.
Moss