upper XLEN-16 bits with 1s. Exceptions: Invalid Included in: Zclsd 35. RV32/64G Instruction Set imm[31:12] rd opcode R-type rs3 funct2 rs2 rs1 111 rd 0010011 ANDI 0000000 shamt rs1 101 rd 0111011 SRAW RV32/RV64 Zifencei Standard Extension imm[11:0] rs1 100 rd 0010011 SRAI 0000000 rs2 rs1 011 rd 0110011 MUL 0000001 rs2 rs1 000 rd 0000011 LH imm[11:0] rs1 010 rd 1110011 CSRRW csr rs1 010 imm[4:0] 0100111 FSQ rs3 11 rs2 rs1 000
skewing