C/C++ Construct RVWMO AMO Mapping atomic <op> release amo <op>.{w|d}.rl atomic <op> amo <op>.{w|d}.aqrl Linux Construct RVWMO LR/SC Mapping atomic_<op>(memory_order_relaxed) amo<op>.{w|d} atomic_<op>(memory_order_acquire) amo<op>.{w|d}.aq atomic_<op>(memory_order_release) amo<op>.{w|d}.rl atomic_<op>(memory_order_acq_rel) amo<op>.{w|d}.aqrl atomic_<op>(memory_order_seq_cst) amo<op>.{w|d}.aqrl C/C++ Construct RVWMO AMO Mapping atomic_<op>(memory_order_relaxed) loop:lr.{w|d}; <op>; sc.{w|d}.aqrl^*; bnez loop OR fence.tso; loop:lr.{w|d}; <op >; sc.{w|d}^*; bnez loop Table 94. Hypothetical mappings from C/C++ primitives to RISC-V primitives. C/C++ Construct RVWMO AMO Mapping atomic_<op>(memory_order_relaxed) amo<op>.{w|d} atomic_<op>(memory_order_acquire) amo<op>.{w|d}.aq atomic_<op>(memory_order_release) amo<op>.{w|d}.rl atomic_<op>(memory_order_acq_rel) amo<op>.{w|d}.aqrl atomic_<op>(memory_order_seq_cst) amo<op>.{w|d}.aqrl C/C++ Construct RVWMO Mapping Load l{b|h|w|d} Load-Reserve lr.{w|d} Store s{b|h|w|d} Store-Release fence rw,w; s{b|h|w|d} atomic_store(memory_order_seq_cst) fence rw,w; s{b|h|w|d} Store-Exclusive sc.{w|d} Store-Release-Exclusive sc.{w|d}.rl dmb fence rw,rw (e) ld a1,0(s1) (b) fence w, w (e) sw t1,0(s2) (f) lw a2,4(s1) xor a3,a2,a2 add s0,s0,a3 (f) sw t1, 4(s0) (b) sw t2,0(s0) ⋮ ⋮ li
misrule