rs2 rs1 010 imm[4:0] 0100011 SD 000000 shamt rs1 101 rd 0110011 OR 0000000 rs2 rs1 rm rd 1010011 FCVT.W.Q 1100011 00001 rs1 rm rd 1010011 FCVT.H.WU 1111010 00000 rs1 rm rd 1001011 FNMSUB.S rs3 00 rs2 rs1 001 rd 1010011 FSGNJX.D 0010101 rs2 rs1 101 rd 0110011 SUB 0000000 rs2 rs1 010 rd 0101111 AMOMIN.D 10100 aq rl rs2 rs1 000 rd 1010011 FCVT.Q.W 1101011 00001 rs1 rm rd 1010011 FEQ.Q 1010011 rs2 rs1 011 imm[4:0] 0100011 SW imm[11:0] rs1 000 rd 0111011 REMW 0000001 rs2 rs1 rm rd 1001011 FNMSUB.S rs3 00 rs2 rs1 rm rd 1010011 FCVT.WU.D 1101001 00000 rs1 001 rd 1010011 FCVT.LU.D 1110001 00000 rs1 000 rd 1010011 FCVT.S.H 0100010 00000 rs1 rm rd 1010011 FCVT.S.D 0100001 00000 rs1 rm rd 1010011 FSQRT.H 0010010 rs2 rs1 010 imm[4:0] 0100111 FSD rs3 01 rs2 rs1 funct3 rd opcode J-type RV32I Base Integer ISA 2.2. Base Instruction Set: LB, LH, LW, LBU, LHU, LWU, LD, FLW, FLD, FLQ, or FLH) or basic store (SB, SH, SW, SD, FSW, FSD, FSQ, or FSH),
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