some external communication mechanism, e.g., a memory-mapped control register. Unprivileged Counter/Timers 0xC00 0xC01 0xC02 0xC03 0xC04 0xC1F 0xC80 0xC81 0xC82 0xC83 0xC84 0xC9F URO URO URO URO URO URO cycle time instret hpmcounter3 hpmcounter4 ⋮ hpmcounter31 cycleh timeh instreth hpmcounter3h hpmcounter4h ⋮ hpmcounter31h Cycle counter for RDINSTRET instruction. Performance-monitoring counter. Performance-monitoring counter. Performance-monitoring counter.
rapacity