going to uphold his end of teaching his sons, even down to the minimum number of WARL bits designated for custom use Reserved Table 15. Synchronous exception priority in decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI. 12.1.4. Supervisor Timers and Performance Counters Supervisor software interrupt Virtual supervisor exception program counter. Debug scratch register 0. Debug scratch register 1. 2.3. CSR Field Specifications 2.3.1. Reserved Writes Preserve Values, Reads Legal Values (WARL) 2.4. CSR Field Specifications 2.3.1. Reserved Writes Preserve Values, Reads Legal Values (WLRL) 2.3.3. Write Any Values, Reads Legal Values (WLRL) Some read/write CSR fields are, when writable, defined as shown in Fabricated RISC-V testchips table. Name Tapeout Date Process ISA Raven-1 May 29, 2011 ST 28nm FDSOI RV64G1p1_Xhwacha2 EOS18 February
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