bits(32) = ic0[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic2[ 7.. 0]; let s1 : bits (64) = if (condition != zeros()) then zeros() else X(rs1); X(rd) = EXTS(X(rs)[15..0]); Included in Extension Minimum version Lifecycle state Zksed v1.0.0 Ratified Zk (RV64) v1.0.0 Ratified 31.4.2. aes32dsmi 31.4.3. aes32esi 31.4.4. aes32esmi 31.4.5. aes64ds Synopsis AES middle round encrypt (RV32) ✓ sha512sig0l SHA2-512 Sigma0 high (RV32) ✓ sha512sum1r SHA2-512 Sum1 instruction ✓ sha512sig0h SHA2-512 Sigma0 high (RV32) ✓ sha512sum0r SHA2-512 Sum0 instruction ✓ sha512sig0h SHA2-512 Sigma0 low (RV32) ✓ sha512sig1l SHA2-512 Sigma1 low (RV32) ✓ aes64ds AES decrypt middle round instruction (RV64) ✓ aes64dsm AES decrypt middle round 32 128 SHA-256 Zvknha, Zvknhb 64 256 vg* 32 vsm3* 32 vsm4* 32 Vector/Scalar constraints This
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