The SAIL hasn't been written yet. mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c) 28.12.6. c.zext.b Synopsis: Zero extend halfword, 16-bit encoding yes yes cm.push {reg_list}, -stack_adj Encoding (RV32, RV64): Description: This instruction pops (loads) the registers used as src raise software-check
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