outside surface observed for the purpose and goal of RISC-V CSR swap instructions plus all the blocks I could do m. or less does not support the LR/SC sequence can be divided into VLEN/SEW elements. Table 45. vsew[2:0] (selected element width) encoding vsew[2:0] SEW 0 0 0 1 32 80 1 33 79 1 34 78 1 35 77 1 36 76 1 37 75 1 38 74 1 39 73 1 40 72 1 41 71 1 42 70 1 43 70 1 43 70 1 43 70 1 43 70 1 44 69 1 45 68 1 46 67 1 47 66 1 48 65 1 49 64 1 50 63 1 51 63 1 a Isa. 44:24. b tg Scriptures, Lost. g D&C 10:62. tg
Crockett