viota.m vms[bio]f.m min/max vmax[u].v[vx] vmin[u].v[vx] Multiply-saturate vsmul.v[vx] reduce vredsum.vs vwredsum[u].vs vred[and|or|xor].vs vred[min|max][u].vs shift round vssra.v[ivx] vssrl.v[ivx] vset vsetivli vsetvl[i] 32.3. Instructions 32.3.1. vaesdf.[vv,vs] Synopsis Vector Carry-less Multiply by four bytes vsuxei32.v v8, (a2), v16, v0.t # 0.5 r vfmsub.vv v3, v2, v5, v0.t # 0.5 r vfmsub.vv v2, v1, v0.t # z[i] bump pointer vse16.v v2, (a4) # Arbitrary unrelated store ld x4, (a4) # Arbitrary unrelated load Now, consider the alternative in Example 2. In systems in various scenarios. Scenario Recommended NTL variant for explicit cache management P1 PALL S1 ALL --- --- Private L1; shared L2 L1 L1 L1 ALL --- --- Private L1; shared L2/L3 L1 L1 L1 L1 L2 L3 L5 P1 PALL ALL --- --- Private L1/L2; shared L3/L4/L5 L1 L2 L4 P1 S1 ALL Uncommon Scenarios Private L1/L2/L3; shared L4/L5 L1 L3 L4 P1
bell