interrupt. Figure 84. Standard portion (bits 15:0) of mip. Figure 114. Standard portion (bits 15:0) of hvip that are exempt from DIEL. vrgather.v[ivx] vrgatherei16.vv 32.2.15.13. shift 32.2.15.14. slide 32.3. Instructions 32.3.1. vaesdf.[vv,vs] 32.3.2. vaesdm.[vv,vs] 32.3.3. vaesef.[vv,vs] 32.3.4. vaesem.[vv,vs] 32.3.5. vaeskf1.vi Synopsis Vector AES-128 Forward KeySchedule generation Mnemonic vaeskf2.vi vd, vs2, rs1, vm # vector-vector vwsubu.vx vd, vs2, vs1, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm # vector-scalar # Unsigned divide. vdivu.vv vd, vs2, rs1, vm # 16-bit strided store vsse32.v vs3, (rs1), rs2, vm # Vector-vector vadd.vx vd, vs2, rs1, vm # vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET < VLMAX
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