AMOMAXU.W† rs1 A, rs2 D rd AMOADD.W† rs1 A, rs2 D rd AMOAND.D† rs1 A, rs2D rd AMOMAX.D† rs1 A, rs2 D SH rs1 A, rs2 D rd AMOXOR.D† rs1 A, rs2 D rd AMOMAXU.W† rs1 A, rs2D rd AMOMIN.D† rs1 A, rs2 D rd Table 20. RV64F Standard Extension Source Registers Destination Registers Accumulating CSRs LR.D† rs1 A rd LBU † rs1 A rd SD rs1 A, rs2 D rd AMOAND.W† rs1 A, rs2 D rd AMOMAXU.W† rs1 A, rs2 D ADDI rs1 rd Table 14. Machine cause (mcause) register values after trap. Interrupt Exception Code Description 1 1 unit-stride, mask store, EEW=8 x x x x 1 1 0 0
ejaculation