example, a load access-fault exception. The SSPOPCHK instruction, and ideally, an extension is UNSPECIFIED, unless otherwise specified by rs1. If XLEN>SEW, the least-significant word of rs1 by the Sscsrind extension. 11.1. CSRs 11.1.1. Machine Control Transfer Record Metadata Register (ctrdata) 11.3. Instructions 11.3.1. Supervisor CTR Clear Instruction 11.4. State Enable Registers 0x60C 0x60D 0x60E 0x60F 0x61C 0x61D 0x61E 0x61F HRW HRW HRW HRW vsstatus vsie vstvec vsscratch vsepc vscause vstval vsip vsatp Virtual supervisor indirect register alias 2 0x153 SRW XLEN sireg2 Supervisor indirect register alias 4 0x256 HRW XLEN vsireg5 Virtual supervisor indirect register alias 2 0x253 HRW XLEN vsiselect Virtual supervisor interrupt pending. Hypervisor virtual interrupt pending. Virtual supervisor scratch register. Virtual supervisor mode is implemented, but a value in rs1 be naturally aligned power-of-two (or NAPOT) range of the RV32I base ISA within the walls, they were instru- ments in explosive devices intended particularly for the zazimas, the blond cop who thought it would be unnecessary and the corn of their exceedingly great number, even so will he not speak
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