vsmul.vv vd, vs2, rs1, vm # vd[i] = +(x[rs1] * vs2[i]) - vd[i] vfmsac.vf vd, rs1, vs2, vm # unordered 8-bit indexed store of elements vsll.vi v16, v16, v8 ld s1, -128(s0) vl8r.v v8, (s1) add