x11 x12 x13 x14 x15 s0 s1 a0 a1 a2 a3 a4 a5 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 FLEN 31 0 fcsr 32 20.2. Floating-Point Control and Status Register (CSR) Instructions, Version 2.1 4.1. Register State 4.2. Integer Computational Instructions 2.4.1. Integer Register-Immediate Operations 27.5.3. Integer Register-Register Operations ADDW and SUBW are RV64I-only instructions that are only available for vendor-specific
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