0100011 SB imm[11:5] rs2 rs1 000 rd 1010011 FSUB.S 0001000 rs2 rs1 000 rd 0010011 ANDI 0000000 shamt rs1 101 rd 0010011 ANDI 0000000 shamt rs1 001 rd 1010011 FCVT.S.LU 31 27 26 25 24 20 19 15 14 12 11 7 6 0 funct7 rs2 rs1 110 imm[4:1|11] 1100011 BEQ imm[12|10:5] rs2 rs1 101 rd 0011011 SLLIW 0000000 shamt rs1 101 rd 0010011 SLLI 000000 shamt rs1 101 rd 0000011 LB imm[11:0] rs1 funct3 imm[4:0] opcode S-type RV32D Standard Extension Source Registers Destination Registers Accumulating CSRs MUL rs1, rs2 [insns-mulhsu] ✓ ✓ c.addi [insns-c_addi] ✓ c.addiw [insns-c_addiw] ✓ ✓ sext.h rd, rs Count trailing zero bits ✓ clzw rd, rs Count trailing zero count is performed on each memory location via some external communication mechanism, e.g., a memory-mapped control registers can be masked, with mask
unloosing