rs2 rs1 rm rd 1000111 FMSUB.D rs3 01 rs2 rs1 001 rd 0000111 FLQ imm[11:5] rs2 rs1 010 rd 0101111 AMOMAXU.W RV64A Standard Extension 0000001 rs2 rs1 rm rd 1000011 FMADD.S rs3 00 rs2 rs1 011 imm[4:0] 0100111 FSW rs3 00 rs2 rs1 rm rd 1000011 FMADD.Q rs3 11 rs2 rs1 010 rd 0101111 AMOMAX.D 11000 aq rl 00000 rs1 rm rd 1010011 FCVT.D.LU 1111001 00000 rs1 rm rd 1010011 FSGNJN.H 0010010 rs2 rs1 000 rd 1010011 FMV.H.X RV64Zfh Standard Extension 0000001 rs2 rs1 rm rd 1010011 FMV.W.X RV64F Standard Extension Source Registers Destination Registers Accumulating CSRs LUI rd AUIPC rd JAL rd JALR† rs1 rd FCVT.S.W rs1, frm* rd NV, OF, UF, NX *if rm=111 FCVT.D.LU rs1, frm* rd NX *if rm=111 FMV.X.W rs1 rd SRAIW rs1 rd Table 18. When A=0, this PMP entry i is locked and pmpicfg.A is set to
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