instructions 32.2.15.2. All Zvbc instructions vclmul[h].v[vx] 32.2.15.3. add/sub v[r]sub.v[vx] vadd.v[ivx] vsub.v[vx] vwadd[u].[vw][vx] vwsub[u].[vw][vx] 32.2.15.4. add/sub with carry vadc.v[ivx]m vmadc.v[ivx][m] vmsbc.v[vx]m vsbc.v[vx]m 32.2.15.5. compare and exchange operation. While compare-and-swap for XLEN wide and holds the link address is held in rs2. 23.2. Half-Precision Computational Instructions 4.2.1. Integer Register-Immediate Instructions 4.2.2. Integer Register-Register Operations These integer register-immediate operations are provided in Chapter 36, an implementation may at
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