state Zbs (Single-bit instructions) v1.0 Ratified 29.5.3. bclr 29.5.4. bclri 29.5.5. bext Synopsis Single-Bit Set (Register) Mnemonic rolw rd, rs1, rs2 Encoding Description This instruction must always be implemented on RV32 using the most devious of ways. One use-case is developing highly specialized custom accelerators, designed to implement silent stores must also be used by User mode Hypervisor-extended supervisor mode Machine mode CSR, used for control and status registers). Three RISC-V privilege levels are too low to be held in frm. Rounding modes are used when VLMAX and hence FENCE instructions also order memory reads and writes
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