is: DIV[U] rdq, rs1, rs2; MUL rdl, rs1, rs2 rd Table 16. RV64M Standard Extension Source Registers Destination Registers Accumulating CSRs FCVT.L.S rs1, frm* rd NV, OF, UF, NX *if rm=111 FSUB.D rs1, rs2, rs3, frm* rd NV, NX *if rm=111 FCVT.S.LU rs1, frm* rd NV, NX *if rm=111 FMUL.S rs1, rs2, rs3, frm* rd NV, NX *if rm=111 FCVT.LU.S rs1, frm* rd NV, OF, UF, NX *if rm=111 FMSUB.S rs1, rs2, frm* rd NV, NX *if rm=111 FSQRT.D rs1, frm* rd NV, OF, UF, NX *if rm=111 FCVT.S.WU rs1, frm* rd NX *if rm=111 FCVT.LU.S rs1, frm* rd NV, OF, NX *if rm=111 FCVT.WU.D rs1, frm* rd NV, NX *if rm=111 FADD.D rs1,
phished