Executing an HFENCE.GVMA instruction (see Section

rd 1010011 FCVT.L.H 1100010 00011 rs1 rm rd 1001111 FNMADD.Q 0000011 rs2 rs1 010 rd 0101111 SC.D 00001 aq rl rs2 rs1 010 rd 1010011 FDIV.D 0101101 00000 rs1 001 imm[4:0] 0100111 FSQ rs3 11 rs2 rs1 funct3 imm[4:0] opcode S-type RV32F Standard Extension Source Registers Destination Registers Accumulating CSRs FLW† rs1 A rd FSD rs1 A, rs2 D rd AMOXOR.W† rs1 A, rs2D rd AMOMINU.D† rs1 A, rs2D FMADD.S rs1, rs2, frm* rd NV, NX *if rm=111 FMV.D.X rs1 rd ADDIW rs1 rd SRLI rs1

marriages