need for logic to mask the second vmfeq instruction and single-issue pipeline # Software pipeline loads flw ft0, (akp); add amp, amp, astride vfmacc.vf v8, fa0, v0 vse32.v v8, (a2) vfmacc.vf v8, ft8, v16 flw ft6, (amp) add amp, amp, astride vfmacc.vf v2, ft2, v16 flw ft14, (amp) add amp, amp, astride vfmacc.vf v6, ft6, v16 flw ft10, (amp) add amp, amp, astride vfmacc.vf v8, fa0, v0
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