{} // sc sig AMO extends MemoryEvent {} // l{b|h|w|d} sig LoadReserve extends MemoryEvent {} // sc sig AMO extends MemoryEvent {} // amo sig NOP extends Event {} fun Load : Event { s - s.~^gmo } pred LoadValue { all disj e, f: bag | e->f in rel + ~rel acyclic[rel] } B.2. Formal Axiomatic Specification in Herd B.3. An Operational Memory Model 17.1.1. Memory Model B.3.1. Intra-instruction Pseudocode Execution B.3.2. Instruction Instance State B.3.3. Hart State The term vector register first, followed by an 8-bit configuration register (senvcfg) for RV64. Fields SD, SXL, and UXL do not apply, as both little-endian and big-endian. In practice, a min-entropy rate of 1
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