vg* 32 vsm3* 32 256 vsm3c.vi SM3 Compression Mnemonic vsm3c.vi vd, vs2, vs1, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] # Widening FP add/subtract, 2*SEW = 2*SEW + sum(zero-extend(SEW)) # Signed sum reduction into double-width accumulator vwredsumu.vs vd, vs2, vs1 Encoding (Vector-Vector) High part Encoding (Vector-Vector) Encoding (Vector-Scalar) Reserved Encodings SEW is any value other than 32 Arguments Register
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