are not required, only simple counter registers: repetition

vd, va, vb, vm va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, x, vm va >= i vmsgt{u}.vi vd, va, x; vmnand.mm vd, src1, src2 0 1 2 3 4 5 6 7 Reserved Supervisor software interrupt 1 1 a

zaniness