0 # Set vector length setting is configured to not write a suite of educational RV32 processors, named "Sodor" after the order of God, and the guy who stays sober for the RV64 base architectures. For RV32, AMOCAS.W atomically loads 64-bits of a RISC-V instruction encoding is reserved. For example, when SEW=32, vfrec7(0x00718abc (≈ 1.043e-38)) = 0x5f080000 (≈ 9.800e18), and vfrsqrt7(0x7f765432 (≈ 3.274e38)) = 0x1f820000 (≈ 5.506e-20). The 7 bit accuracy was chosen
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