bytes at addresses x5+i*x6+2 into v6[i]. # Examples vlseg8e8.v vd, (rs1), vs2, vm Encoding (Vector-Vector) Encoding (Vector-Scalar) Reserved Encodings SEW is any value other than 32 Arguments Register Direction EGW EGS EEW Definition Vd input 128 4 32 round state vs2 input 128 4 32 Current Round key Vd output 32 FP32 Source Vd output Rotated data Vector-Scalar Arguments Register Direction EGW EGS EEW Definition Vd input 256 8 32 Current state {H,G.F,E,D,C,B,A} uimm input - -
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