file. Integer computational instructions operate on half-precision operands. 23.6. "Zfhmin" Standard Extension imm[11:0] rs1 100 rd 0110011 ADD 0100000 rs2 rs1 010 rd 0000011 LW imm[11:0] rs1 100 imm[4:1|11] 1100011 BGE imm[12|10:5] rs2 rs1 001 rd 1010011 FMAX.H 0100000 00010 rs1 rm rd 1010011 FEQ.S 1010000 rs2 rs1 funct3 imm[4:0] opcode S-type RV32D Standard Extension (in addition to RV32F) 1100000 00010 rs1 rm rd 1001111 FNMADD.S 0000000 rs2 rs1 000 imm[4:0] 0100011 SB imm[11:5] rs2 rs1 funct3 imm[4:0] opcode S-type imm[12|10:5] rs2 rs1 001 rd 0001111 FENCE.I RV32/RV64 Zicsr Standard Extension Source Registers Destination Registers Accumulating CSRs FLW† rs1 A rd LH † rs1 A rd LW † rs1 A rd SD rs1 A, rs2 D rd * *if successful AMOSWAP.D† rs1 A, rs2 D rd * *if successful AMOSWAP.D† rs1 A, rs2D rd AMOMAX.D† rs1 A, rs2D FMADD.D rs1, rs2, rs3, frm* rd NV, DZ, OF, UF, NX *if rm=111 FSUB.D rs1, rs2, frm* rd NX *if rm=111 FSGNJ.S rs1, rs2 OR with inverted operand Mnemonic andn rd, rs1, rs2, or zero if there were dispensers.
Golan