rs2 rs1 001 rd 1010011 FMIN.D 0010101 rs2 rs1 011 rd 0110011 ADD 0100000 rs2 rs1 111 rd 0010011 SLTI imm[11:0] rs1 funct3 rd opcode R-type rs3 funct2 rs2 rs1 010 rd 1010011 FSGNJN.H 0010010 rs2 rs1 000 rd 1010011 FCVT.S.D 0100001 00000 rs1 000 rd 1010011 FEQ.Q 1010011 rs2 rs1 010 rd 1010011 FCVT.L.D 1100001 00011 rs1 rm rd 1010011 FCLASS.D 1100001 00000 rs1 rm rd 1010011 FSGNJ.H 0010010 rs2 rs1 funct3 imm[4:0] opcode S-type RV32Zfh Standard Extension for Load-Reserved/Store-Conditional Instructions Complex atomic memory operation in that which p. not; 32:8
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