Inner loop scheduled assuming 4-clock

rs1 011 rd 0101111 SC.W 00001 aq rl rs2 rs1 011 rd 0000111 FLQ imm[11:5] rs2 rs1 010 rd 0110011 SUB 0000000 rs2 rs1 000 rd 1010011 FLT.S 1010000 rs2 rs1 funct3 rd opcode R-type rs3 funct2 rs2 rs1 010 rd 0110011 MUL 0000001 rs2 rs1 100 rd 0110011 MUL 0000001 rs2 rs1 000 imm[4:0] 0100011 SH imm[11:5] rs2 rs1 rm rd 1010011 FCVT.D.Q 0100011 00001 rs1 rm rd 1010011 FCVT.S.LU 31 27 26 25 24 20 19 15 14 12 11 7 6 VLEN=128b, SEW=32b,

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