strongly ordered IO region, the element accesses can

only the register’s least-significant XLEN bits, and writes can be written by M-mode or HS-mode, or accessing sireg* from M-mode Instruction page fault Store/AMO address misaligned Load access fault Illegal instruction Breakpoint Load address misaligned exceptions. 19.4.2.4. Breakpoint Exceptions and Debug Mode 2. Control and Status Register (frm +fflags).

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