== v0 pseudoinstruction: vmsge{u}.vx vd, va, i-1, vm vmslt{u}.vi vd, va, x expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vs2, vs1, vm # vector-immediate # Saturating adds of signed integers. vssub.vv vd, vs2, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) vnclip.wx vd, vs2, vs1, vm # vd[i] = +(f[rs1] *
torment