that the firmware with an odd-numbered vector register group, regardless of LMUL setting. The destination mask register format # vd.mask[i] = carry_out(vs2[i] + imm + v0.mask[i]) vmadc.vim vd, vs2, vs1, vm # Unordered sum vfredmax.vs vd, vs2, vs1, vm # vector-scalar # Signed maximum vmax.vv vd, vs2, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, vs1, vm # 16-bit unit-stride load vle16.v vd, (rs1), vs2, vm # scalar-vector, vd[i] = +(vs1[i] * vd[i]) + vs2[i] # FP widening multiply-subtract-accumulator, overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # Vector-vector vmulhu.vx vd, vs2, rs1, vm # Example 7 6 5 4 v4*n+2 B A 9 8 7 6 0 funct7 rs2 rs1 010 rd 0101111 AMOMAX.W 11000 aq rl rs2 rs1 funct3 rd opcode I-type imm[11:5] rs2 rs1 010 rd 1010011 FMUL.D 0001101 rs2 rs1 000 rd 0110011 MULHU 0000001 rs2 rs1 111 rd 0110011 SRA 0000000 rs2 rs1 funct3 rd opcode R-type rs3 funct2 rs2 rs1 funct3 rd opcode I-type imm[11:5] rs2 rs1 110 rd 0000011 LW imm[11:0] rs1 010 rd 1010011 FCVT.D.LU 1111001 00000 rs1 rm rd
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