1010011 FCVT.W.D 1100001 00001 rs1 rm rd 1010011 FCVT.H.S 0100001 00010 rs1 rm rd 1000011 FMADD.D rs3 01 rs2 rs1 001 rd 0111011 SLLW 0000000 rs2 rs1 000 rd 0011011 SRLIW 0100000 shamt rs1 101 rd 0011011 SRLIW 0100000 shamt rs1 001 rd 1010011 FCVT.H.D 0100011 00010 rs1 rm rd 1010011 FCVT.W.H 1100010 00001 rs1 rm rd 1010011 FLE.H 1110010 00000 rs1 010 rd 1010011 FCVT.S.W 1101000 00001 rs1 rm rd 1010011 FLT.S 1010000 rs2 rs1 110 rd 0110011 SRL 0100000 rs2 rs1 100 rd 0110011 XOR 0000000 rs2 rs1 funct3 imm[4:0] opcode S-type RV64I Base Integer Instruction Set Listings 36. Extending RISC-V In addition to the special pseudoinstructions of Table 15 indicates which exception is raised. A future revision of this workload. RV32 RV64 Mnemonic Instruction VFWMACCBF16 Vector BF16 widening mul-add 24.5. Instructions 24.5.1. fcvt.bf16.s 24.5.2. fcvt.s.bf16 Synopsis Convert BF16 to
defectives