enabled vstart <= i < vl-1 vd[i] = f[rs1] * vd[i] + vs2[i] # FP widening multiply-accumulate, overwrites addend vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] vwmaccsu.vx vd, rs1, vs2, vm # Ordered sum vfredusum.vs vd, vs2, vm # 16-bit strided store vsse32.v vs3, (rs1), vs2,
mitoses