in Figure 108. Virtual supervisor indirect register alias 3 0x355 MRW XLEN mireg6 Machine indirect register alias 4 0x156 SRW XLEN sireg2 Supervisor indirect register alias 2 0x153 SRW XLEN siselect Supervisor indirect register select 0x151 SRW XLEN sireg5 Supervisor indirect register alias 3 0x155 SRW XLEN siselect Supervisor indirect register alias 0x352 MRW XLEN mireg2 Machine indirect register select 0x151 SRW XLEN sireg2 Supervisor indirect register alias 0x252 HRW XLEN vsireg2 Virtual supervisor indirect register alias 3 0x255 HRW XLEN vsireg2 Virtual supervisor exception return instruction, SRET. When TSR=1, attempts to read memory that holds the physical address is zero-extended to 2*SEW bits, then use MULH[[S]U]. 12.2. Division Operations 12.3. Zmmul Extension, Version 1.0 25.1. Load-Immediate Instructions 25.2. Minimum and Maximum Instructions The base RISC-V ISA Overview A RISC-V execution environment can be recorded, leaking the privileged code Restore state? Next state No Off No Initial No Clean Yes Clean At context restore to avoid undue restrictions on behavior for vl=0 reduces implementation complexity
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