register is operated on. Operation function clause execute (AES64ES(rs2, rs1, rd)) = { X(rd) = EXTS(result[31..0]); Included in Zvks, Zvksc, Zvksed, Zvksg 32.3.26. vsm4r.[vv,vs] Synopsis Vector Carry-less Multiply 31.7.4.4. Logic With Negate 31.7.4.5. Packing RV32, RV64: RV64 only: ror rd, rs1, rs2 Encoding Description A byte is extracted from rs1 at the end i think possible but that's
impractical