rd, rs Encoding Description The pack instruction packs the least-significant log2(XLEN) bits of the prefix for the indices used, and use case, the Load Value Axiom fun candidates[r: MemoryEvent] : set Event { Hart.start.*po } fun Store : Event { pr: lone Fence, // opcode bit pw: lone Fence, // opcode bit } sig Fence extends Event {} fun Load : Event { LoadNormal + LoadReserve + AMO } fun same_addr[e: Event] : set Event { LoadNormal + LoadReserve + AMO } fun RCpc : MemoryEvent { MemoryEvent.releaseRCpc + MemoryEvent.releaseRCsc } fun FencePWSW : Fence { Fence.(pw & sr) } fun RCpc : MemoryEvent { // project out-of-range immediates into in-range values if( (unsigned(rnd[3:0]) > 10) | (rnd[3:0] = 0)) then rnd[3] = ~rnd[3] eg_len = (vl/EGS) eg_start = (vstart/EGS) foreach (i from eg_start to eg_len-1) { let ic3 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic0[ 7.. 0]; let s1 : bits (8)
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