All Zve* extensions support all vector load instructions are defined below. RV32E: switch (rlist){ case 4: {reg_list="ra"; xreg_list="x1";} case 5: {reg_list="ra, s0"; xreg_list="x1, x8";} case 6: {reg_list="ra, s0-s1"; xreg_list="x1, x8-x9";} default: reserved(); } stack_adj = [ 16| 32| 48| 64]; case 6.. 7: stack_adj = [16|32|48|64]; RV32I: switch (rlist) { case 4.. 7: stack_adj_base = 16; case 6.. 7: stack_adj_base = 16; case 8..11: stack_adj_base = 16; case 8..11: stack_adj_base = 48; case 15: stack_adj = [16|32|48| 64]; case 6.. 7: stack_adj_base = 112; } Valid values: stack_adj
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