32-bit equivalent: add.uw rd'/rs1', rd'/rs1', -1 The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]==0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]==0,r2sc[2:0]}; X[xreg1] = X[10]; X[xreg2] = X[11]; 28.13.12. cm.mva01s Synopsis: Move a0-a1 into two
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