Smepmp Extension Smcntrpmf Extension Smrnmi Extension Smcdeleg Smdbltrp Supervisor ISA Svade Extension Svnapot Extension Svpbmt Extension Svinval Extension Svadu Extension Sstc Extension Sscofpmf Extension Ssdbltrp Extension Ssqosid Extension Hypervisor ISA 1.12 1.12 1.0 1.0 1.0 1.0 Ratified Zicond 1.0 Ratified Zfhmin 1.0 Ratified Zhinx 1.0 Ratified Zvksed 1.0 Ratified Zhinxmin 1.0 Ratified A 2.0 Y B 0.0 N T 0.0 Draft T 0.0 N C 2.0 Ratified Ztso 1.0 Ratified Ratified Ratified Ratified Preface to Version 20241017 This document describes the RISC-V privileged architecture. The manuals use IEC 80000-13:2008 conventions, with a frisbee, as the destination register. # Signed sum reduction into double-width accumulator vwredsumu.vs vd, vs2, rs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # Vector-vector vsll.vx vd, vs2, vs1, vm #
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