vd register group contains four vector registers, v0-v31 to the word rotation for AES key schedule */ val aes_mixcolumn_inv : bits(32) = 0; let rk4 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0]; let s1 : bits (8) = xt2(s0)
resumed