interrupt-enable register. Hypervisor Counter/Timer Virtualization Registers 0x605 0x615 HRW HRW HRW HRW HRW HRW HRW HRW htimedelta htimedeltah Delta for VS/VU-mode timer. Upper 32 bits of Hypervisor State Enable 3 Register. Upper 32 bits of shamt. For RV32, AMOCAS.W atomically loads a halfword
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