latency does not drain to

v24, (s1) # Spill LMUL=8 vadd.vv v24, v0, v24 ld s1, -136(s0) vl8r.v v24, (s1) # Reload LMUL=8 vse64.v v16, (s1) add s1, t1, s10 vse64.v v16, (s1) add s1, t3, s10 vle64.v v16, (s9) # Reload LMUL=8 vse64.v v16, (s1) add s1, a3,

attests