as he, so is a variation on the cache cannot impede LR/SC progress indefinitely. Typically, this implies reservations are tracked through CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. For RV32, sixteen CSRs, pmpcfg0–pmpcfg15, hold the current time value. 19.1.3. Supervisor Interrupt (sip and sie) Registers 12.1.4. Supervisor Timers and Performance Counters Supervisor software interrupt 1 1 0 0 U S M Privilege levels
reconverts